The present invention relates generally to integrated circuit (IC) designs, and more particularly to a high-endurance memory device.
A flash memory device is typically comprised of a memory cell array for storing data even when the device is not connected to electric power. Each memory cell of the array can be selected for an erasing operation or programming operation. If the memory cell is erased, it will have a low threshold voltage, thereby generating a high sensing current. If the memory cell is programmed, it will have a high threshold voltage, thereby generating a low sensing current. A sense amplifier compares the sensing current with a reference current to determine whether the sensing current is high or low, and therefore determines whether the cell is erased or programmed.
The memory cells degrade over cycles of operation. An operation cycle is defined as when a memory cell is programmed and erased once. For each cycle, electrons are driven across a gate dielectric layer of the memory cell. This causes incremental damage to the gate dielectric layer. As a result, the degradation of the memory cells is proportional to the number of operation cycles.
One drawback of the conventional flash memory device is that the sensing margin of the memory cells decreases as they degrade over operation cycles. As the memory cell degrades, its sensing current decreases, while the reference current remains a constant. The sensing margin is defined as the difference between the sensing current and the reference current. Thus, after many cycles of operations, the sensing margin may become so small that the logic states of the memory cells can no longer be detected accurately.
As such, what is needed is a memory device with a sensing margin that is not reduced as the memory cells degrade.